The present invention relates to the field of electronic circuit design as performed by, for example an IC design house.
An IC is a semiconductor device that includes many electronic components (e.g., transistors, diodes, inverters, etc.). These electrical components are interconnected to form larger scale circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC.
Design engineers create an IC by transforming a circuit description of the IC into a geometric description called a “layout”. To create an IC layout, design engineers typically use electronic design automation (“EDA”) applications. These EDA applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. EDA applications create layouts by using geometric shapes that represent different materials and devices on integrated circuits.
Due to the increase of clock frequencies and design sizes clock tree construction has become a challenging problem in the design of ICs. Clock trees are also described as clock distribution networks which distribute clock signals from a root or source to all sinks that need it. Roots are typically the pins of any kind of logic gates including PLLs (Phase Locked Loops). Sinks are typically the clock pins of latches.
In order to ensure proper synchronization between various parts of an integrated circuit design each clock signal should reach all sinks on an integrated circuit at certain target arrival time windows. Thus, the time required for a clock signal to travel from its root to any sink should hit the target arrival time window for all paths it follows through the global clock tree. The time required for a clock signal to work its way through the global clock tree from its root to a sink depends on many factors, such as the length of conductors in the path, the number of buffers the clock signal must pass through, the switching delay of each buffer, the amount of attenuation which the clock signal incurs between the buffer stages, and the load each buffer must drive.
A typical application of clock tree construction is in the design of ASICs (Application Specific Integrated Circuit), for example. When producing an ASIC for a customer it is usual to insert test circuits in the ASIC design. The test circuits may not change the functional design of the ASIC. The test circuits are used during a manufacturing and bring-up process of a chip. In a manufacturing process they are used to separate error-free chips from bad ones. During a bring-up process test circuits are used to analyze error conditions etc. Then the problem exists, that the modified ASIC design comprising the additional test logic needs to be functionally equivalent to the ASIC design without the test logic.
For the equivalence check between two logic designs Boolean equivalence checker (BEC) tools exist, e.g. IBM Verity. However, such BEC tools can vary the equivalence of Boolean circuits only. Checker tools that are able to compare sequential logic circuits are still not ready for usage in today's design processes. A BEC tool needs to compare output signal values for equal input signal values between two designs. Therefore, a 1:1 mapping between the signal names of the two designs is required.
A specific approach to add additional test logic to an ASIC design is therefore one that introduces fixed circuits in clock trees, hence allowing a 1:1 mapping between two designs. A fixed circuit is a circuit that exists in a clock tree and must not be cloned or removed. It may be a fixed-in-location circuit in addition, in which case its placement must not be altered. Multiple fixed circuits and/or fixed-in-location circuits may exist in a clock tree. Generally, there are various reasons why fixed circuits in a clock tree are needed.
As mentioned above some chip test structures require certain circuits in a clock tree which may not be changed or removed. VMACs (virtual macros) are an example. VMACs are wrapper circuits that are introduced when using SRAM (static random access memory) circuits on an integrated circuit in the IBM Cu-65 technology. They implement special test structures that allow at-speed testing of the SRAM (Static Random Access Memory) circuits for example.
In another scenario, some parts of chip logic may be switched off during chip operation mainly to safe power. For such logic pieces simply the clock signal is switched off. This is done by gating circuits, usually AND or OR circuits. For these circuits it is required that they are not cloned because the gating signal will be created by some logic which is already optimized with respect to timing before clock tree construction. Therefore, it is not desired that clones of these circuits are created because this would have a negative impact on the timing of the gating signal. Also the placement of the gating circuits needs to be fixed because it is important that a gating circuit is placed close to the gating logic and the clock tree sinks, i.e. the fixed circuits are fixed-in-location circuits in this case.
Furthermore, in hierarchical designs the macro level input drivers are fixed circuits.
The general problem of constructing a configuration of at least one logic structure, preferably of clock tree construction, is the task of parallel and serial repowering of one or multiple logic structures such that the given target arrival time windows at all sinks are achieved. For zero-skew clock trees the target is to let the signal arrive at all sinks at the same time. In both cases this process is called “aligning”. Further tasks are that all newly created buffers, inverters and circuits are placed legally, that limits for slew and capacity values are not exceeded and that the Boolean structure of a logic structure, preferably a clock tree, is not altered. Assumed that all these conditions are fulfilled it is a task to minimize the latency of the configuration.
Clock tree construction, especially in the presence of fixed circuits in between clock trees or clock tree parts usually is a difficult and manual task. With current methods a sub-clock tree after a fixed circuit is built separately. After the main clock tree has been built manual effort is needed to fix the skew between different clock trees that has been created by this approach.
For example, in Held S., Korte B., Maβberg J., Ringe M., Vygen J.: “Clock Scheduling and Clock Tree Construction for High Performance ASICs”, Proceedings of the International Conference on Computer Aided Design, 2003, pp. 232-239, a method of building a clock tree and the calculation of the arrival times is disclosed. In the first part of the article a method for providing an optimally scheduled clock tree is introduced. Then the construction of the clock tree itself is performed in several iterations. Starting from the sinks of the skew-scheduled clock tree a new vertex of the clock tree to be constructed is generated as predecessor of an active vertex. The successors of the new vertex are computed using a greedy clustering strategy and will become inactive, i.e. their position is fixed. The predecessor itself will become an active vertex now. The iterations are terminated when all remaining active vertices can be connected to the source, i.e. the root of the clock tree.